Ing. Filip Baum

This article proposes a novel approach to enhancing the low-voltage ride-through capability of doubly-fed induction generator wind turbines using a dynamically modulated braking resistor (DBR) connected in series with the stator windings. Unlike conventional DBR-based methods that focus primarily on mitigating electrical transients, the proposed approach emphasizes maintaining the generator’s electromagnetic torque at its prefault level during grid voltage dips. The DBR resistance is calculated in real time based on analytical expressions derived from the system’s model. By properly selecting the DBR resistance during the fault, the excess mechanical power that cannot be transferred to the grid is dissipated within the resistor, allowing the generator torque to remain constant during the fault, which helps maintain rotor speed and mitigate electrical transients. The proposed strategy is validated through both simulation and experimental results under symmetrical fault conditions, demonstrating superior torque stability, reduced current transients, and improved postfault recovery compared to fixed-resistance DBR schemes.

Discontinuous PWM (DPWM) strategies are widely used in Voltage-Source Inverters (VSIs) due to reduced switching losses and improved harmonic performance at higher modulation indexes. However, DPWMs with discontinuous Zero-Sequence Signals (ZSS) can cause current spikes at clamping instants, which depend on the modulation index and load parameters. In the literature, this behavior is often attributed to the rapid changes in ZSS. This paper demonstrates that the current spikes are primarily caused by improper modulator implementation on Digital Signal Processors (DSPs), which introduces an unintended active vector instead of a zero vector at the end of a positive bus clamp for a given phase. The issue arises because PWM modules operate as set-reset units based on a timer and compare values, unlike analog comparators, which react instantaneously. We propose a simple solution using an auxiliary compare register, which is effective for most DSPs. The solution's effectiveness is demonstrated on a VSI-fed 12-kW induction machine controlled by a C2000 Texas Instruments DSP.

This paper investigates the impact of DC-link voltage imbalance on the output voltage accuracy of Dual-Inverter (DI) topologies, which are increasingly relevant in highperformance electric mobility systems due to their efficient DCbus utilization and potential for switching loss reduction via advanced modulation techniques. A modulation strategy that clamps one inverter and modulates the other is analyzed, with attention given to its assumption of equal DC-link voltages. It is shown that voltage asymmetry distorts the inverter voltage hexagon, leading to significant errors in synthesized voltage vectors and introducing waveform discontinuities. Analytical expressions for these errors are derived and validated through simulations, highlighting the limitations of conventional modulation approaches and the need for improved strategies under non-ideal conditions.

This paper extends the concept of using dynamic braking resistors (DBRs) in series with the stator of doubly-fed induction generators (DFIGs) to improve low-voltage ride-through (LVRT) performance, specifically under asymmetrical grid faults. Although previous studies have demonstrated the effectiveness of fixed or discrete-valued DBRs in mitigating electrical transients, mechanical issues such as torque loss remain mostly underexplored. In this work, we leverage independent control of the resistance in each stator phase by means of pulse-width modulation to maintain generator torque and cancel the negative sequence component of the grid voltage. By shaping the DBR voltage drop through asymmetric resistances, the resulting negative sequence voltage opposes that of the grid, reducing torque oscillations and enabling more stable DFIG operation during unbalanced faults. Analytical derivations and simulation results validate the proposed control strategy.

The Dual-Inverter (DI) topology, composed of two two-level Voltage Source Inverters (VSIs), offers a promising alternative to multilevel inverters. It enables multilevel output capability, efficient DC-link voltage utilization, and inherent fault tolerance. However, it involves twice as many switching events compared to a conventional two-level VSI, resulting in higher power losses. Existing modulation strategies either achieve moderate loss reduction with simple implementation or offer greater efficiency at the cost of increased control complexity. This paper proposes a novel modulation strategy, termed SixStep+GDPWM, that combines simple implementation with effective switching loss reduction. The method operates one inverter in a pseudo six-step mode to minimize switching events, while the second inverter is continuously modulated using a clamped waveform. The clamped interval can be phase-shifted relative to the output current, similar to the Generalized Discontinuous PWM (GDPWM) approach used in classical two-level VSIs. The proposed strategy is verified through simulations, demonstrating reduced switching losses across a wide range of operating points while preserving waveform quality and implementation simplicity.

Many electric drives, such as railway traction machines, are designed to be operated in an overmodulation region and in six-step mode, where the motor voltage waveform is distorted by low-order harmonics. The Selective Harmonic Elimination (SHE) method is an effective solution to reduce these unwanted harmonics. The SHE algorithm requires solving complex transcendental equations, traditionally tackled using algebraic or genetic algorithms. Historically, these equations were pre-solved, and the resulting switching angles were incorporated into microprocessors through Look-Up Tables (LUTs) and were selected based on the reference voltage. However, with the decreasing cost of electronic components, Field-Programmable Gate Arrays (FPGAs) have become a viable option for real-time computation of these equations. This paper validates the effectiveness of the SHE method in the common three-phase two-level Voltage Source Inverter (VSI) by implementing an off-line FPGA-in-the-Loop setup, integrated with MATLAB ® and Simulink ® environments, where the VSI and load are modeled. The Verilog FPGA computational modules designed in this paper were rigorously simulated and, upon achieving successful results in behavioral simulations, they were synthesized and deployed on a development board featuring a System on Chip (SoC) with an integrated FPGA.

This paper introduces an innovative overmodulation strategy for a dual two-level inverter topology featuring galvanically isolated DC-links and accommodating arbitrary distribution of DC-bus voltages. In such a configuration, the uneven distribution of DC voltages gives rise to 12 additional fundamental voltage vectors compared to the conventional two-level inverter, effectively enabling the topology to function as a five-level inverter. The primary innovation of our proposed method lies in its ability to transition from linear modulation to what we term an 18-step operation – an improved multilevel square-wave operation of the inverter. This extended operational range is achieved through a hybrid space vector PWM approach, a well-established technique in the context of two-level inverters. Moreover, this paper presents a crucial nonlinear gain compensation characteristic essential for real-time control applications. To validate the effectiveness of our approach, we conducted experiments using a custom 15-kW GaN dual inverter. These experiments included the implementation of a straightforward V/Hz control of a 12-kW induction motor supplied by the dual inverter. The results of our experiments confirm the strategy's effectiveness, demonstrating superior current waveform quality and a seamless transition from linear modulation mode to the 18-step operation.

This paper introduces a novel overmodulation strategy tailored for dual-inverter topologies with galvanically isolated DC-links and evenly distributed DC-link voltage. The core contribution of the paper is the utilization of the multilevel capabilities of the dual-inverter topology. At the maximum modulation index, the presented overmodulation method achieves what is referred to as a 12-step operation. The 12-step operation improves the voltage waveform and offers superior harmonic performance compared to the conventional 6-step operation. The utilized approach leverages a hybrid Space Vector Pulse Width Modulation (SVPWM) method, a well-established technique in two-level inverters, to achieve this extended operation range. Furthermore, the paper presents a nonlinear gain compensation characteristic vital for real-time motor control applications and provides a comparative analysis of the modulation's harmonic performance. The proposed approach is validated through simulations and experiments. The experiments were conducted using a custom inverter based on Gallium-Nitride (GaN) transistors where simple volt/hertz control of an induction motor was programmed. The results of these experiments affirm the strategy's effectiveness, showcasing superior current waveform quality and a smooth transition from linear mode to 12-step operation while keeping a simple implementation of the algorithm.

The increasing popularity of electric drives employing an isolated dual-inverter (DI) topology is motivated by their superior DC-link voltage and power utilization, fault-tolerant operation, and potential for multilevel operation. These attributes are significant in battery-powered transportation, such as electric vehicles and aviation. Given the considerable freedom in modulation and control of the DI topology, this paper researches the impact of reference voltage vector distribution between the two individual inverters. The study also evaluates the influence of two well-established asynchronous modulation strategies—Space Vector PWM (SVPWM) and Depenbrock’s Discontinuous Modulation (DPWM1). Since simulation tools nowadays play a crucial role in power electronics design and concept verification, the results are based on extensive and detailed models in Matlab/Simulink. Employing the basic field-oriented control of a 12 kW induction motor with precisely parameterized SiC switching devices for accurate loss calculation, this research reveals the possibility of significant energy savings at multiple operating points. Notably, optimal efficiency is achieved when one inverter operates up to half of the nominal speed while the other solely establishes a neutral point for the winding. Moreover, the results highlight DPWM1 as a superior strategy for the DI topology, showcasing reduced converter losses. Overall, it is shown that the system’s losses can be significantly reduced just by the design of the voltage vector distribution in the drive’s operating range and the modulation strategy selection.

The dual-inverter topology is a key solution for high-performance motor drives, offering reliability and efficient DC-bus voltage utilization. This paper focuses on the isolated DC source configuration, known for its fault tolerance and suitability for applications like electric vehicles. Unlike common DC source setups, it eliminates the zero-sequence current path. This study explores the harmonic properties of popular carrier-based asynchronous modulation techniques (SVPWM, DPWM1, and DPWM2) in dual-inverter systems. While these techniques are well-studied in conventional inverters, their behavior in dual-inverter setups remains underexplored. The investigation includes different reference vector distributions and compares results with conventional inverters. The findings enhance our understanding of harmonic behavior in dual-inverter configurations, providing insights for optimizing motor drives and power electronics applications.

To address the gap in the tooling software for verifying Field Programmable Gate Array (FPGA) design, this paper introduces a Verilog implementation of a fully synthesizable unit for monitoring values of internal wires and registers. The unit samples an arbitrary number of internal signals and packages them into a Universal Asynchronous Receiver Transmitter (UART) message. Even when analysing multiple bit values only three FPGA board pins are required to transmit and receive messages using UART, in contrast to the conventional hardware logic analyzers where numerous pins are needed. The message is then sent from the FPGA to the Real-Time Monitor (RTM) application running on a host PC. Developed using the Rust programming language, the application ensures reliability, performance, memory safety, and efficiency. The resource utilization of the unit, deployed on the Gowin GW1NR-9 27 MHz chip, is presented. The unit, along with the RTM application, can be efficiently utilized for verifying arbitrary Verilog designs or employing them as an acquisition or monitoring hardware-software product.

The Dual-Inverter (DI) emerges as a viable solution to address the ever-growing demands of electric drives, encompassing fault tolerance capability, waveform quality, superior DC-bus voltage utilization, and multilevel operation. The DI with isolated DC sources eliminates the path for zero sequence current (ZSC), thereby enabling the implementation of various modulation strategies. This paper introduces two bus-clamping modulation strategies aimed at minimizing switching losses for DI with isolated DC sources. The effectiveness of these modulation strategies is validated using a DI model in the MATLAB/Simulink environment, incorporating SiC MOS-FETs transistors parameterized in accordance with the manufacturer’s datasheet. An induction machine with a rated power of 12 kW serves as the load for DI.

The Dual Inverter (DI) stands out as an optimal solution for electric drives and aviation, offering multilevel capabilities, high fault tolerance, waveform quality, and efficiency. Particularly, in configurations with isolated DC sources, a diverse array of modulation techniques can be effectively implemented. This paper compares the 60 ◦ Discontinuous Pulse-Width Modulation (DPWM)–well established technique for conventional two-level inverters, against the proposed Near State Pulse-Width Modulation (NSPWM) for DI, specifically examining their impact on switching losses. The assessment relies on a comprehensive MATLAB/Simulink model of the DI, incorporating SiC MOSFETs transistors parameterized in accordance with the manufacturer’s specifications. Additionally, a 12 kW squirrel cage induction motor is employed as the load for simulation purposes.

This paper investigates the most significant voltage distortion effects present in GaN-based Dual Inverter (DI) topology. Dual Inverters have emerged as promising solutions for various applications in electric drives, offering advantages such as superior DC-bus voltage utilization and multilevel operation capability. These advantages can be further enhanced when equipped with wide bandgap power devices such as GaN. However, despite the superior switching speeds of GaN devices compared to their traditional Si counterparts, they still exhibit nonlinear behavior and delayed current-dependent switching properties, resulting in distortion in the inverter output voltage, especially in high-frequency applications. Therefore, this paper aims to analyze and analytically describe the output voltage distortion arising from deadtime and delayed switching in GaN-based DIs. A simple mathematical model is proposed to accurately characterize this type of voltage distortion, which is then experimentally validated using a custom laboratory DI prototype.

Mathematical models of induction motor (IM) used in direct field‑oriented control (DFOC) strategies are characterized by parametrization resulting from the IM equivalent circuit and model‑type selection. The parameter inaccuracy causes DFOC detuning, which deteriorates the drive performance. Therefore, many methods for parameter adaptation were developed in the literature. One class of algorithms, popular due to their simplicity, includes estimators based on the model reference adaptive system (MRAS). Their main disadvantage is the dependence on other machines’ parameters. However, although typically not considered in the respective literature, there are other aspects that impair the performance of the MRAS estimators. These include, but are not limited to, the nonlinear phenomenon of iron losses, the effect of necessary discretization of the algorithms and selection of the sampling time, and the influence of the supply inverter nonlinear behavior. Therefore, this paper aims to study the effect of the above-mentioned negative aspects on the performance of selected MRAS estimators: active and reactive power MRAS for the stator and rotor resistance estimation. Furthermore, improved reduced‑order models and MRAS estimators that consider the iron loss phenomenon are also presented to examine the iron loss influence. Another merit of this paper is that it shows clearly and in one place how DFOC, with the included effect of iron losses and inverter nonlinearities, can be modeled using simulation tools. The modeling of the IM and DFOC takes place in MATLAB/Simulink environment.