Lidé

Ing. Tomáš Musil, Ph.D.

Všechny publikace

High Performance IIR Filter FPGA Implementation Utilizing SOS Microcode Core

  • DOI: 10.14311/TEE.2019.2.022
  • Odkaz: https://doi.org/10.14311/TEE.2019.2.022
  • Pracoviště: Katedra elektrických pohonů a trakce
  • Anotace:
    This paper discusses the methods of optimal IIR filter FPGA implementation. The methods are focused on the reduction of occupied resources and increasing data throughput. Higher demands on an internal controller complexity are successfully solved by utilizing programmable microcode controller. The novelty of SOS core and its capabilities are presented and different variants of SOS core are assessed. The workflow of IIR filter design using MATLAB considering rounded coefficient method is demonstrated.

The first hardware MSC algorithm implementation

  • Autoři: Fábera, V., Ing. Tomáš Musil, Ph.D., Řada, J.
  • Publikace: Neural Network World. 2017, 27(6), 541-555. ISSN 1210-0552.
  • Rok: 2017
  • DOI: 10.14311/NNW.2017.27.029
  • Odkaz: https://doi.org/10.14311/NNW.2017.27.029
  • Pracoviště: Katedra elektrických pohonů a trakce
  • Anotace:
    This paper describes the first attempt of hardware implementation of Multistream Compression (MSC) algorithm. The algorithm is transformed to series of Finite State Machines with Datapath using Register-Transfer methodology. Those state machines are then implemented in VHDL to selected FPGA platform. The algorithm utilizes a special tree data structure, called MSC tree. For storage purpose of the MSC tree a Left Tree Representation is introduced. Due to parallelism, the algorithm uses multiple port access to SDRAM memory.

Za stránku zodpovídá: Ing. Mgr. Radovan Suk