Lidé

Ing. Ondřej Šubrt, Ph.D.

Všechny publikace

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

  • DOI: 10.15598/aeee.v17i3.3061
  • Odkaz: https://doi.org/10.15598/aeee.v17i3.3061
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, such as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump Design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc., are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were found based on the time response characteristics of the pump sub-block. The goals include both maximize the voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc.

A program procedure for estimation of the cross-coupled charge pump properties

  • DOI: 10.23919/AE.2018.8501429
  • Odkaz: https://doi.org/10.23919/AE.2018.8501429
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents the computional algorithm that is used for prediction of the cross-coupled charge pump static and dynamic properties. The calculation method is based on the state-space model of the charge pump for each phase of the clock signal. State equations are drawn from the symbolic relationships of the pump stage as an analog functional block using BSIM equations for long channel MOSFET. The algorithm was programmed in Maple SW and calculated values were compared with transistor-level circuit characteristics. The analysis results show high accuracy of the mentioned method, which allow to reflect many real effects compared to the equivalent digital model description. The algorithm will be used for synthesis procedure together with the application of formulae for optimal design circuit without long-time simulation process.

Complex model description and main capacitor sizing for the cross-coupled charge pump synthesis process

  • DOI: 10.2478/jee-2018-0049
  • Odkaz: https://doi.org/10.2478/jee-2018-0049
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents a dynamic part of the pump stage model of the cross-coupled charge pump. The complex model has been used for both the estimation of the N -stage pump properties in a wide range of the input parameters and derivation of equations for synthesis process, as the main capacitor sizing, which is also mentioned in the article. Dynamic part of the model (pump stage capacitances) is determined from Ward’s capacitance piece-wise model through the BSIM MOSFET model equations. Main capacitor and load capacitor sizing are based on the time response characteristics fulfilling the system behavior in time. Guideline on the MOS transistor sizing as the nonlinear main pump capacitor and specification of the diode transistor for the design process are also clarified. The characteristics of the proposed circuit have been verified in the professional design environment Mentor graphics and analysis algorithm based on the state-space description of the inner complex model was programmed in Maple SW. The main benefit is to offer the alternative way of the charge pump synthesis by using the complex model and symbolic description of all formulae to find the required pump parameters without long-time simulation process.

New Variant of a Negative 4-phase Charge Pump

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Charge pump (CP) is a micropower alternative to conventional DC/DC converters. CPs have a small size and an easier integrability than conventional DC/DC converters. Nowadays, CPs became an integral part of low-voltage integrated circuits that contain some blocks with specific voltages. An example is non-volatile memories (Flash) that use programming voltage a greater than 10 V, but these circuits use power supply voltage about 1 V. Thus, these systems must integrate a positive CP that increases power supply voltage to an appropriate programming voltage. Required voltage gain of a CP can be decreased with a usage of modified programming scheme [1] that is based on negative bias. This paper is concentrated on a new concept of negative CP and comparison of this new concept with standard Dickson Charge Pump (DCP). The key parameters as voltage gain, rise time, number of elements, chip area and efficiency are compared by simulations executed by Mentor Graphics.

Performance optimization methods for switched-capacitor biquadratic filters

  • DOI: 10.2478/jee-2018-0050
  • Odkaz: https://doi.org/10.2478/jee-2018-0050
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    A class of computer-aided optimization methods based on Differential Evolution (DE), Particle Swarm Optimization (PSO) and Nelder Mead algorithms applied to a switched-capacitor (SC) filter circuit design are investigated. Comparisons of these algorithms applied to a 4th order biquadratic two-channel filter bank CMOS design on 0. 35 μm technology are made. The frequency responses of the biquadratic filters must match ideal responses in a finite number of iterations with a limited number of ”particles”. The original and derived methods are evaluated on the base of their convergence progress and their reliability over different starting populations. An optimal design approach based on combining algorithms is derived as a more suitable and more reliable method for SC circuit optimization.

SC Filter Optimization Performance by Hybrid Simplex Algorithm

  • DOI: 10.1109/SMACD.2018.8434885
  • Odkaz: https://doi.org/10.1109/SMACD.2018.8434885
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    The paper investigates the performance of the Nelder-Mead (NM) and Differential Evolution (DE) hybrid algorithm applied to switched capacitor (SC) filter optimization. The performance is investigated on a design of four biquadratic filters and the results are compared to the original algorithm performances and other hybrid algorithms performances

Analýza přechodových dějů v křížově vázané nábojové pumpě

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    V tomto článku je uveden odhad velikosti dvou složek ztrát v obvodu křížově vázané nábojové pumpy používané pro napájení nízkopříkonových obvodů. V úvodu jsou shrnuty diskutované složky pumpovacích ztrát, následně je vysvětlena metodika postupu jejich odhadu v reálném obvodu. V hlavní části jsou uvedeny výchozí rovnice odvozené na základě analýzy elementárních bloků uvedené topologie, včetně ověření finálních vztahů v simulačním prostředí Mentor Graphics. Závěrečná kapitola je věnována popisu zjednodušeného nelineárního modelu jedné buňky a simulaci charakteristických vlastností v N-stupňové struktuře, včetně porovnání výsledků se skutečným zapojením pumpy. Přínosem práce je použití odvozených vztahů pro syntézu a optimalizaci zapojení bez nutnosti použití časově náročných optimalizačních algoritmů.

Description of the Functional Blocks for the Cross-Coupled Charge Pump Design Algorithm

  • DOI: 10.23919/AE.2017.8053594
  • Odkaz: https://doi.org/10.23919/AE.2017.8053594
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents the circuit model that is used for the cross-coupled charge pump design algorithm. Symbolic description of the pump stage model as an analog functional block for high-voltage application is firstly discussed. Design process has been done by using simplified BSIM model equations assuming the long channel MOSFET. Characteristics have been verified by ELDO Spice and compared with the found relationships. Static and dynamic parameters of the subcircuit have been tested in two-stages structure by LT Spice simulator. Analysis results show the consistency between model and real circuits characteristics under given conditions. Complex model provides the reliable results for significantly smaller strange capacitances in comparision with the main pump capacitances. The model can be used for design and prediction of the pump parameters without long-time simulation process. The strong inversion region of MOSFET is expected, thus equations are correct for other MOSFET models that are used in chip design (PSP).

Fibonacci Charge Pump Design, Test and Measurement

  • DOI: 10.23919/MEASUREMENT.2017.7983554
  • Odkaz: https://doi.org/10.23919/MEASUREMENT.2017.7983554
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    The charge pumps are used in many areas of electronic industry for generating higher (or negative) voltage than a power supply. Our article is focused on the development two variants of the charge pump in discrete form. We consider Dickson charge pump and the Fibonacci charge pump that have to meet several criteria listed below. These charge pumps were designed and verified by simulations then they were realized in discrete form and their parameters were verified by measurement.

Fitting simulated and measured parameters of Dickson charge pump

  • DOI: 10.23919/MEASUREMENT.2017.7983553
  • Odkaz: https://doi.org/10.23919/MEASUREMENT.2017.7983553
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    The charge pumps are used in many areas of electronic industry for generating higher (or negative) voltage than a power supply. Our article is focused on the development Dickson charge pump in discrete form. This charge pump was designed and realized on PCB. The key parameters were measured and verified with the parameters from simulation after fitting models of the used electronic components.

Guidelines on the switch transistors sizing using the symbolic description for the cross-coupled charge pump

  • DOI: 10.13164/re.2017.0781
  • Odkaz: https://doi.org/10.13164/re.2017.0781
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents a symbolic description of the design process of the switch transistors for the cross-coupled charge pump applications. Discrete-time analog circuits are usually designed by the numerical algorithms in the professional simulator software which can be an extremely time-consuming process in contrast to described analytical procedure. The significant part of the pumping losses is caused by the reverse current through the switch transistors due to the continuous-time voltage change on the main capacitors. The design process is based on the analytical expression of the time response characteristics of the pump stage as an analog system with using BSIM model equations. The main benefit of the article is the analytical transistors sizing formula so that the maximum voltage gain is achieved. The diode transistor is dimensioned for the pump requirements, as the maximal pump output ripple voltage, current, etc. The characteristics of the proposed circuit have been verified by simulation in ELDO Spice. Results are valid for N-stage charge pump and also applicable for other model equations as PSP, EKV.

New Discrete Fibonacci Charge Pump Design, Evaluation and Measurement

  • DOI: 10.1515/msr-2017-0013
  • Odkaz: https://doi.org/10.1515/msr-2017-0013
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper focuses on the practical aspects of the realisation of Dickson and Fibonacci charge pumps. Standard Dickson charge pump circuit solution and new Fibonacci charge pump implementation are compared. Both charge pumps were designed and then evaluated by LTspice XVII simulations and realised in a discrete form on printed circuit board (PCB). Finally, the key parameters as the output voltage, efficiency, rise time, variable power supply and clock frequency effects were measured.

Design Aspects of the SC Circuits and Analysis of the Cross-Coupled Charge Pump

  • DOI: 10.1109/AE.2016.7577265
  • Odkaz: https://doi.org/10.1109/AE.2016.7577265
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents some real properties of the cross-coupled charge pump that is used in lowpower microelectronic integrated systems operating with high voltage (FLASH, EEPROM memories). SC-circuits characterization and design aspects are firstly discussed. Theoretical analysis of the cross-coupled charge pump with accompanying equations has been done. Some real properties have been simulated by ELDO Spice and compared with these assumptions. Simulation results show discrepancy between calculation and simulated parameters due to significant pumping losses that have been discussed in detail. Discontinuity of the output voltage through input parameters is very important finding that complicates the development of the real model for design purposes.

Design Rules of the CMOS Inverter for Voltage Converters

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper presents a description of the dominant characteristics of the CMOS inverter, which is used for voltage converters–charge pumps applications. This circuit controls transport charge between main capacitors to create a higher DC voltage. The significant part of the pump losses is caused by the inverter cross current. This current flows through the inverter in transition state and discharges the capacitor, therefore decreases the pump voltage gain. The CMOS inverter design is based on the analog block description for high-voltage integrated circuits using BSIM model equations. The main benefit of this article is derivated analytical relationship between width and length of the NMOS and PMOS transistors to achieve the static power minimization. The derivation has been performed based on the sensitivity analysis. The design relationship are applicable to the other MOSFET models, as EKV. The characteristic of the proposed circuit has been verified by simulation in ELDO Spice. Analysis results show that the cross current is reduced by ten times in comparison with the value of the standard digital inverter (with symmetrical voltage transfer characteristics). This improvement was achieved while keeping relatively large area of both transistors satisfying the dynamic properties.

Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes

  • DOI: 10.1515/msr-2016-0032
  • Odkaz: https://doi.org/10.1515/msr-2016-0032
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Charge pumps are circuits that produce the voltage higher than supply voltage or negative voltage. Today, charge pumps became an integral part of the electronic equipment. The integration of charge pumps directly into the system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is reduced by many phenomena. This paper is focused on the question of efficiency of proposed variant of the charge pump. In this article, the efficiency dependence on a number of stages, output current, clock frequency and MOSFETs sizes was simulated by Eldo. The aim of this study is to determine the MOSFETs sizes and theirs influence to efficiency and the output voltage. Complex optimization of the charge pump circuit will follow in further text.

Modelovaní funkčních bloků křížově vázané nábojové pumpy

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    V tomto článku je uveden rozbor buňky křížově vázané nábojové pumpy používané pro napájení nízkopříkonových obvodů. V úvodu jsou uvedeny základní složky pumpovacích ztrát a jejich důsledky v reálném obvodu. V hlavní části je provedena optimalizace základních bloků-invertoru a spínače za účelem dosažení maximálního napěťového zisku. Optimalizační proces zahrnuje analytický popis a elementární simulace příslušných charakteristik (statických, dynamických) těchto bloků v profesionálním návrhovém prostředí Mentor Graphics, se zahrnutím reálných prvků dostupných v knihovně MGC Design Kit. Modely dílčích bloků jsou sestaveny na základě rovnic BSIM modelu MOSFET tranzistorů, zjednodušených pro konkrétní aplikaci. Přínosem práce jsou jednak získané analytické vztahy pro návrh invertoru a spínače a jednak vytvořeny ekvivalentní nelineární model buňky nábojové pumpy, jež je použitelný pro sestavení návrhového algoritmu.

Vliv hodinového kmitočtu a velikosti tranzistorů na účinnost inovativní nábojové pumpy

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Nábojové pumpy jsou obvody, které vytváří napětí vyšší velikosti, než odpovídá napájecímu napětí. V současnosti se nábojové pumpy staly nedílnou součástí elektronických zařízení. Integrace nábojových pump přímo do systému dovolují výrobcům napájet komplexní systémy s mnoha specifickými napájecími požadavky z jednoho napájecího zdroje. Účinnost nábojových pump je však omezována mnoha nepříznivými vlivy. Tento příspěvek je zaměřen na otázku účinnosti uvedené varianty nábojové pumpy. Pomocí simulací provedených v prostředí Eldo je zkoumána účinnost v závislosti na počtu stupňů pumpy, odebíraném proudu, taktovacím kmitočtu a rozměrech použitých MOSFE tranzistorů. Smyslem této práce je určení vlivu rozměrů MOSFE tranzistorů na výslednou účinnost a hodnotu výstupního napětí. Komplexní optimalizace obvodu pumpy bude provedena v navazující práci, kdy již nebude třeba nahlížet na méně podstatné vlivy.

Analýza nábojové pumpy CTS-2

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    V příspěvku je uveden rozbor nábojové pumpy typu CTS-2 vhodné pro napájení nízkopříkonových obvodů. Článek poukazuje na problematiku návrhu a charakterizaci vlastností uvedeného typu pumpy. V článku je popsán základní princip včetně rozboru neideálních vlastností. Následně jsou ukázány dosažené parametry reálného zapojení pumpy simulované v profesionálním návrhovém prostředí a jejich srovnání s teoretickými předpoklady. Závěrečná část uvede čtenáře do základů modelování.

Charge Pump Design for Use in NVM Device Test and Measurement

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Today, the emerging technology to fabricate deep-submicron Non-Volatile Memories (NVMs) requires extensive use of efficient methods for measurement and test. A high-voltage (HV) generator must be used to invoke NVM test modes, either placed on-chip or used from external. Our article focuses on the development of the Charge pump, being a core of such high-voltage generator. We consider an on-chip variant for the purpose of NVM measurement and test, the HV generator has to meet several criteria listed above. In our article we will particularly take into account the design criteria for the Charge pump to be used in such HV generator and the ways how to optimize its properties.

Optimization Methods for Switched Capacitor Circuits

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    The paper investigates the performance of the Differential Evolution (DE) and Particle Swarm Optimization (PSO) algorithm for SC filter Optimization. In order to improve their performance the three algorithm based on their combination are proposed. The performance is investigated on the design of switched capacitor biquadratic filters and the resulting performance and limitations are discussed.

Simulace nábojové pumpy za účelem optimalizace jejích vlastností

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Současné technologie používané pro výrobu submikronových nonvolatilních pamětí vyžadují silné nasazení prostředků pro měření a testování. Pro aktivaci testovacího režimu je nutný „vysokonapěťový“ generátor, který je buď zabudován na čipu, nebo je připojen z vnějšku. Náš příspěvek se věnuje návrhu nábojové pumpy zabudované do čipu, která představuje jádro vysokonapěťového generátoru. Kritéria, která musí takový vysokonapěťový generátor splňovat, jsou uvedena níže. V našem příspěvku jsou částečně zmíněna i návrhová kritéria pro nábojové pumpy a možnosti, pomocí kterých lze optimalizovat jejich vlastnosti.

Porovnání integrovatelných nábojových pump pro paměťové čipy

  • Autoři: Matoušek, D., Martinek, P., Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: IV. Letní doktorandské dny 2014. Praha: ČVUT FEL, Katedra teorie obvodů, 2014. pp. 13-16. ISBN 978-80-01-05506-9.
  • Rok: 2014
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Trendem současnosti je maximální redukce spotřeby elektronických zařízení. Napájení z baterií akcentuje požadavky nízkého napájecího napětí a nízkého příkonu. Nicméně stále existuje mnoho elektronických bloků, které nejsou schopny pracovat správně při sníženém napájecím napětí. Alternativou k použití konvenčních DC/DC měničů jsou pak nábojové pumpy. Nábojové pumpy mají malé rozměry, snadno se integrují a jsou schopny pracovat na vyšších kmitočtech než klasické měniče. Nábojové pumpy jsou proto v současnosti nedílnou součástí integrovaných obvodů, které obsahují bloky požadující napájecí napětí desítek voltů. Přímá integrace nábojových pump přímo do systémů, které požadují specifická napájecí napětí, dovoluje napájet takto komplexní systémy z jediného zdroje. Účinnost nábojových pump je snížena vlivem prahového napětí, rozptylové kapacity, časových konstant způsobených odporem kanálu atd.. Tento příspěvek je věnován porovnání několika architektur nábojových pump s nově vytvořenou variantou. Pomocí simulačního programu Mentor Graphics, Eldo verze 2010.2b jsou porovnány klíčové parametry různých architektur nábojových pump.

A Contribution to Nyquist-Rate ADC Modeling - Detailed Algorithm Description

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Valenta, M., Martinek, P.
  • Publikace: Radioengineering. 2012, 21(1), 252-257. ISSN 1210-2512.
  • Rok: 2012
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    In this article, the innovative ADC modeling algorithm is described. It is well suitable for nyquist-rate ADC error back annotation. This algorithm is the next step of building a supportive tool for IC design engineers. The inspiration for us was the work [2]. Here, the ADC behavior is divided into HCF (High Code Frequency) and LCF (Low Code Frequency) separated independent parts. This paper is based on the same concept but the model coefficiens are estimated in a different way only from INL data. The HCF order recognition part was newly added as well. Thanks to that the HCF coefficients number is lower in comparison with the original Grimaldi's work (especially for converters with low ratio between HCF and "random" part of INL). Modeling results are demonstrated on a real data set measured by ASICentrum on charge-redistribution type SAR ADC chip. Results are showed not only by coefficient values but also by the Model Coverage metrics. Model limitations are also discussed.

An FPGA Algorithm Development for an Improved Servo-Loop Method

  • Autoři: Židek, J., Mullane, B., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012. pp. 151-154. ISBN 978-1-4673-1185-4.
  • Rok: 2012
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with the FPGA (Field-Programmable Gate Array) implementation of the improved servo-loop algorithm, which has been already described in [1]. It is a new part of our testing environment for ADCs (Analog-to-Digital Converters). The article is focused especially on the algorithm function and features. FPGA resources, measurement time consumption and recommended necessary improvements are also briefly discussed.

Developing Model-Based Design Evaluation for Pipelined A/D Converters

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow.

A Contribution to Nyquist-Rate ADC Modeling

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Valenta, M., Martinek, P.
  • Publikace: CD-ROM Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: Brandenburg University of Technology at Cottbus, 2011. pp. 127-130. ISBN 978-1-4244-9754-6.
  • Rok: 2011
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    In this article, innovative ADC modeling algorithm is described. It is well suitable for nyquist-rate ADC error back annotation. The inspiration for us is the work [2]. Here, the ADC behavior is divided into HCF (High Code Frequency) and LCF (Low Code Frequency) separated part. Close connection of this model type to circuit representation of ADC is the reason why we choose them. The main difference between [2] and our approach is in the purpose. Our algorithm is oriented especially in converters with low order of HCF or converters with low ratio between HCF and "random" part of INL. The algorithm proves the highest efficiency in the previously mentioned case; however, it is also applicable to general error modeling related to ADC transfer characteristic. Moreover, we have designed efficient HCF order recognition part. Modeling results are demonstrated on a real data set measured by ASICentrum on charge-redistribution type SAR ADC chip.

Advanced Design and Optimization Methods of Analog and Mixed-signal Integrated Systems

  • Autoři: Valenta, M., Martinek, P., Ing. Ondřej Šubrt, Ph.D., Židek, J., Urban, T., Burian, L.
  • Publikace: Workshop 2011,CTU Student Grant Competition in 2010 (SGS 2010). Praha: ČVTVS, 2011.
  • Rok: 2011
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with design of signal pre-processing chain that integrates all subsidiary topics together. The mentioned chain simply consist of analog amplifier anti-aliasing filter and analog to digital converter (ADC). The article will provide a comprehensive preview of the design of such a complex electronic chain from its top level, over the filter synthesis and AD converter modeling, to the application of advanced active building blocks such as operation amplifiers (OA), transconductance amplifiers (OTA), current conveyors (CC), band-gap references (BGR). The optimization method, which is used almost in all steps of our design is an integral part of this article. The novelty of our approach consist in several new topologies on block- or transistor-level, advanced evolutionary optimization methods utilized to adjust the parameters of proposed blocks and the original idea of one-chip CMOS implementation of whole pre-processing unit.

An FPGA Implementation for ADC INL Measurement using the Servo-loop Method

  • Autoři: Židek, J., Mullane, B., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Proceedings of the 8th International Conference on Digital Technologies 2011. Žilina: Slovenská elektrotechnická společnost, 2011. pp. 194-198. ISBN 978-80-554-0437-0.
  • Rok: 2011
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with the new part of our testing environment for A/D converters and describes the FPGA implementation of the improved servo-loop algorithm. The article is focused especially on the algorithm function and features. FPGA resources and measurement time consumption are also briefly discussed.

AN INNOVATIVE ALGORITHM FOR ADC MODELING

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P., Valenta, M.
  • Publikace: Electronic Devices and Systems, IMAPS CS International Conference 2011 Proceedings. Brno: VUT v Brně, FEKT, 2011. pp. 174-179. ISBN 978-80-214-4303-7.
  • Rok: 2011
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    In this article, innovative ADC modeling algorithm is described. It is well suitable or Nyquist-rate ADC error back annotation. The ADC behavior is divided into HCF (High Code Frequency) and LCF (Low Code Frequency) separated part. Close connection of this model type to circuit representation of ADC is the reason why we choose them. Our algorithm is oriented especially on converters with low order of HCF or converters with low ratio between HCF and "random" part of INL. The algorithm proves the highest efficiency in the previously mentioned case; however, it is also applicable to general error modeling related to ADC transfer characteristic. Moreover, we have designed efficient HCF order recognition part. Modeling results are demonstrated on a real data set measured by ASICentrum on charge-redistribution type SAR ADC chip. Focus of the paper is to introduce algorithm body with the stress on the key model extraction stages. Least but not last the experimental results are dis

Analysis and Design Procedure of LVLP Sub-bandgap Reference: Development and Results

  • Autoři: Urban, T., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Radioengineering. 2011, 20(1), 239-244. ISSN 1210-2512.
  • Rok: 2011
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This work presents an thorough analysis and design of a low-voltage low-power voltage reference circuit with sub-bandgap output voltage. The outcome of the analysis and the resulting design rules are universal and it is supposed to be general and suitable for similar topologies with just minor modifications. The general analysis is followed by a selection of specific topology. The given topology is analyzed for particular parameters which are standard industrial circuit specifications. These parameters are mathematically expressed, some are simplified and equivalent circuits are used. The analysis and proposed design procedure focuses mainly on versatility of the IP block. The features of the circuit suit to low-voltage low-power design with less than 10μA supply current draw at 1.3V supply voltage.

Innovative ADC modeling algorithm

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Valenta, M., Martinek, P.
  • Publikace: Digital Technologies 2010. Žilina: TU v Žilině, 2010. pp. 100-103. ISBN 978-80-554-0304-5.
  • Rok: 2010
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    In this article, innovative ADC modeling algorithm is described. It is well suitable for nyquist-rate ADC error back anotation. This algorithm is the next step of building a supportive tool for IC design engineers. The inspiration for us is the work Mr. Grimaldi. Here, the ADC behavior is devided into HCF (High Code Frequency) and LCF (Low Code Frequency) separated part. Close connection of this model type to circuit representation of ADC is the reason why we choose them. The main difference between Grimaldi and our approach is in the purpose. Our algorithm is oriented especially on converters with low order of HCF or converters with low ratio between HCF and "random" part of INL. Moreover, we have designed efficient HCF order recognition part. Modeling results are demonstrated on a real data set measured by ASICentrum on charge-redistribution type SAR ADC chip.

Versatile Engine for Virtual Testing of ADC/DAC Non-Linearity

  • DOI: 10.1109/SM2ACD.2010.5672327
  • Odkaz: https://doi.org/10.1109/SM2ACD.2010.5672327
  • Pracoviště: Katedra teorie obvodů, Katedra mikroelektroniky
  • Anotace:
    We propose a novel versatile engine for behavioral or transistor-level design verification of data converters. This tool is dedicated to IC designers to verify static performance of the converters during their design. It is based on advanced Servo-Loop method presented in and extended by features such as innovative DAC testing method. The environment proposed supports various converter resolutions and several types of digital coding.

A/D Converter Design Evaluation Engine in MGC Environment

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: MEASUREMENT 2009 - Proceedings of the 7th International Conference on Measurement. Bratislava: Institute of Measurement Science, 2009. pp. 235-238. ISBN 978-80-969672-1-6.
  • Rok: 2009
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Environment for testing static parameters of analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for to educate students in working with modern CAD tools. The source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). The core of our proposal is based on Servo-Loop with improved search algoritm. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.

AN INNOVATIVE VERIFICATION APPROACH FOR NYQUIST-RATE A/D CONVERTERS

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Electronic Devices and Systems, IMAPS CS International Conference 2009 Proceedings. Brno: VUT v Brně, FEI, 2009. pp. 369-374. ISBN 978-80-214-3933-7.
  • Rok: 2009
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Environment for testing static parameters of analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. The source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). The core of our proposal is based on Servo-Loop with improved search algoritm. The simulation outputs are curves of static INL and DNL.

An Innovative Verification Approach For Nyquist-rate A/D Converters - Algorithm and Implementation

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Environment for testing static parameters of analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. The source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). The core of our proposal is based on Servo-Loop with improved search algoritm [1]. The simulation outputs are curves of static INL and DNL. Here, we focus mainly on algorithm and implementation of testing interface.

Experience in Virtual Testing of RSD Cyclic A/D converters

  • Autoři: Kubař, M., Ing. Ondřej Šubrt, Ph.D., Martinek, P., prof. Ing. Jiří Jakovenko, Ph.D.,
  • Publikace: Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09). Los Alamitos: IEEE Computer Society Press, 2009. p. 178-181. ISSN 2334-3133. ISBN 978-1-4244-3339-1.
  • Rok: 2009
  • DOI: 10.1109/DDECS.2009.5012123
  • Odkaz: https://doi.org/10.1109/DDECS.2009.5012123
  • Pracoviště: Katedra teorie obvodů, Katedra mikroelektroniky
  • Anotace:
    This paper deals with the ADC non-linearity extraction using a newly developed Virtual Testing Environment (VTE). The VTE proposed is built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment. The Servo-Loop method used is aimed at the non-linearity extraction of static ADC transfer curve; in this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. Powerful capabilities of the proposed VTE were successfully confirmed by a large set of behavioral and transistor-level simulations in Spectre.

Novel Design Evaluation Engine for A/D Converters

  • Autoři: Židek, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: 2009 Ph.D. Research in Microelectronics and Electronics. Piscataway: IEEE, 2009. pp. 240-243. ISBN 978-1-4244-3732-0.
  • Rok: 2009
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Environment for testing analog-to-digital converters is presented in this article. It is a novel concept of powerful engine suitable for design and verification of generic type ADCs in Mentor Graphics IC Studio software. Source code of each block of the design is written in Verilog-A which offers relatively effortless portability on different design systems (e.g. Cadence). This approach brings to IC design engineers easy to use supportive tool. The core of our proposal is based on Servo-Loop with improved search algorithm [1]. The simulation outputs are curves of static INL and DNL. A part of article deals with the example of simple Flash ADC testing.

VIRTUAL TESTING METHOD FOR STATIC ADC NON-LINEARITY - RSD CYCLIC A/D CONVERTER CASE

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Kubař, M., Martinek, P., prof. Ing. Jiří Jakovenko, Ph.D.,
  • Publikace: XIX IMEKO World Congress 2009 - Fundamental and Applied Metrology. Lisbon: Instituto Superior Técnico/Instituto de Telecomunicaçoes Portugal, 2009. p. 690-693. ISBN 978-963-88410-0-1.
  • Rok: 2009
  • Pracoviště: Katedra teorie obvodů, Katedra mikroelektroniky
  • Anotace:
    One of the recent approaches to test A/D converter performance is the so-called Servo-Loop Method. This method is aimed at the non-linearity extraction of static ADC transfer curve. In this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. In this paper, we establish a Virtual Testing Environment (VTE) built on Verilog-A implementation of the Servo-Loop unit fully integrated into Cadence design environment.

A Virtual A/D Converter Testbench for Educational Purpose - Development and Results

  • DOI: 10.2478/v10048-008-0019-6
  • Odkaz: https://doi.org/10.2478/v10048-008-0019-6
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with a new concept of virtual testing engine for analogue-to-digital converters (ADCs). The whole system consists of program procedures to extract the most important ADC errors expressed in terms of integral and differential non-linearity (INL and DNL). The developed testbench is especially suitable for educational purpose because of modular conception of the system. The proposed testing engine is implemented in Maple™, bringing an ideal possibility to make a complex system for the simulations of ADC at the virtual level as well as at the circuit level.

Advanced Modeling and Design Evaluation Procedure applied to Pipelined A/D Converter

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed in term of integral and differential nonlinearity.

Developing Model and Design Evaluation Procedure For Pipelined A/D Converters

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed in term of integral and differential non-linearity.

Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Struhovský, P., Martinek, P., doc. Dr. Ing. Jiří Hospodka,
  • Publikace: Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 (DDECS'08). Los Alamitos: IEEE Computer Society Press, 2008. p. 283-286. ISBN 978-1-4244-2276-0.
  • Rok: 2008
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with the implementation issues of building Virtual Testing Environment (VTE) for performance extraction of A/D converters. Here, the term "virtual" implies to the fact that the ADC testing is done yet in the circuit design on a base of an ADC model capable to capture the ADC error sources occurring in the integrated circuit structure. The first part of the contribution concerns significant properties of two proposed VTE algorithm implementations, the first one employing Verilog-A behavioral module and the second which is created in Maple environment with built-in libraries for circuit analysis. The performance of both VTE implementations is evaluated at system-level and by simulation of residual non-linearity with an ideal ADC model.

A Contribution to Advanced Extraction Methods for Static ADC Non-linearity

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P., Wegener, C.
  • Publikace: 2007 IEEE Instrumentation and Measurement Technology Conference Proceedings. Warsaw: IEEE, 2007. pp. 49-52. ISSN 1091-5281. ISBN 1-4244-0589-0.
  • Rok: 2007
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    One of the recent approaches for A/D converter performance extraction is the so-called Servo-Loop method. In this paper, we build an improved version of this method targeted to full transistor-level circuit simulation of static integral and differential non-linearity. In comparison with the conventional implementation, the Servo-Loop version proposed was enhanced by a powerful search algorithm. Subsequently, this paper deals with the description of a versatile Servo-Looper tool developed in Verilog-A language suitable for direct co-operation with most of the analog and mixed-signal simulators used in industry. Powerful capabilities of the proposed Servo-Looper tool were successfully confirmed by a large simulation set performed on a full custom ADC design example. The presented paper brings the most significant results of the ADC simulation procedure.

A Contribution to Advanced Extraction Methods for Static ADC Non-linearity

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P., Wegener, C.
  • Publikace: IMTC/2007 IEEE Instrumentation and Measurement Technology Conference Proceedings. Warsaw: IEEE, 2007. pp. 49-52. ISBN 1-4244-1080-0.
  • Rok: 2007
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    One of the recent approaches for A/D converter performance extraction is the so-called Servo-Loop method. In this paper, we build an improved version of this method targeted to full transistor-level circuit simulation of static integral and differential non-linearity. In comparison with the conventional implementation, the Servo-Loop version proposed was enhanced by a powerful search algorithm. Subsequently, this paper deals with the description of a versatile Servo-Looper tool developed in Verilog-A language suitable for direct co-operation with most of the analog and mixed-signal simulators used in industry. Powerful capabilities of the proposed Servo-Looper tool were successfully confirmed by a large simulation set performed on a full custom ADC design example. The presented paper brings the most significant results of the ADC simulation procedure.

A Powerful Extension of Servo-Loop Method for Simulation-based A/D Converter Testing

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P., Wegener, C.
  • Publikace: 12th TC4 International Workshop on ADC Modelling and Testing. Iasi: CERMI Publishing House, 2007. pp. 57-62. ISBN 978-973-667-264-4.
  • Rok: 2007
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with the performance aspects of Virtual Testing Environment (VTE) built for A/D converter performance extraction. Here, the term "virtual" implies the fact that the ADC testing is done yet in the circuit design to identify and possibly optimize the major error sources at transistor-level. The procedure of virtual testing is aided by behavioral and system models so as to streamline the decomposition of nonidealities present in the real ADC structure.

A Prospective Approach for Simulation-based Non-linearity Extraction of A/D Converters

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Our work proposes a prospective approach for non-linearity extraction of analog-to-digital converters (ADCs) based on the simulation of ADCs. The testing engine is implemented in MAPLE and consists of program procedures for extracting ADC errors expressed in term of integral and differential non-linearity (INL and DNL). As the performance extraction algorithms we use the Servo-Loop and Histogram method. In our work, we deal with the Nyquist-rate ADCs, and in particular with converters employing the successive approximation technique. The novelty of our solution is the use of effective search algorithms and improved convergence properties, significantly accelerating the conversion.

A virtual A/D converter testbench for educational purpose

  • Autoři: Struhovský, P., Ing. Ondřej Šubrt, Ph.D., doc. Dr. Ing. Jiří Hospodka, Martinek, P.
  • Publikace: Measurement 2007 - Proceedings of 6th International Conference on Measurement. Bratislava: Institute of Measurement Science of the SAS, 2007. pp. 98-101. ISBN 978-80-969672-0-9.
  • Rok: 2007
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with a new concept of virtual testing engine for analog-to-digital converters (ADCs). The whole system consists of program procedures to extract the most important ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The developed testbench is especially suitable for education purpose because of modular conception of the system. The testing engine proposed is implemented in MAPLE, bringing an ideal possibility to make a complex system for simulating of ADC on the virtual-level as well as on the circuit-level.

Comparison of Virtual Testing Environments for Extracting A/D Converter Non-linearity

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper deals with the performance aspects of Virtual Testing Environment (VTE) built for A/D converter performance extraction. Here, the term "virtual" implies the fact that the ADC testing is done yet in the circuit design to identify and possibly optimize the major error sources at transistor-level.

Developing Virtual ADC Testing Environment in MAPLE

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    This paper proposes an innovative concept of a virtual testing environment for analog-to-digital converters (ADCs) applying a suitable conjunction of two performance extraction algorithms - the Servo-Loop and Histogram method. The testing engine proposed is implemented in MAPLE and consists of program procedures to extract ADC errors expressed in term of integral and differential non-linearity (INL and DNL). The novelty of our solution is the use of effective search algorithm and improved convergence properties resulting in a significant reduction of the simulation time.

SPICE OpAmp macromodels for WinSpice

  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    Our work deals with macromodels of operational amplifiers (OpAmp) for computer simulations. The reason of usage a macromodel for simulation is the time and cost saving. The greatest advantage of a macromodel is the fact that it allows to analyze the behavior of a specific circuit part without necessity to build the whole system. This is an effective approach for evaluation and acceleration of electronic system design.

A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006. pp. 108-112. ISBN 1-4244-0184-4.
  • Rok: 2006

Developing Model-Based Design Evaluation for Algorithmic A/D Converters

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P., Wegener, C.
  • Publikace: IMEKO - XVIII World Congress and IV Brazilian Congress of Metrology. Rio de Janeiro: IMEKO, 2006.
  • Rok: 2006

Development of Virtual A/D Converter Testing Environment in MAPLE

Model-Based Testing and Design Evaluation of Mixed-Signal Devices: an ADC Example

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P., Wegener, C.
  • Publikace: Electronic Devices and Systems - IMAPS CS International Conference 2006. Brno: Vysoké učení technické v Brně, 2006. pp. 113-118. ISBN 80-214-3246-2.
  • Rok: 2006

High Performance Analogue Periphery and Testing Environment for Use in Switched-Current and Switched-Capacitor Circuits

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Maršík, J., Martinek, P.
  • Publikace: Digital Technologies 2005. Žilina: Slovenská elektrotechnická společnost, 2005. pp. 90-95. ISBN 80-8070-486-4.
  • Rok: 2005

A Novel Design Evaluation Equipment and Analogue Periphery Implemented to SC and SI Circuits

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Maršík, J., Martinek, P.
  • Publikace: Proceedings of the IEEE IC Test Workshop. Cork: Cork Institute of Technology, 2004. pp. 9-14. ISBN 0-9548342-0-8.
  • Rok: 2004

High-Precision Circuit Techniques Suitable for Analogue Front-End of Switched-Capacitor and Switched-Current Systems

  • Autoři: Maršík, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Proceedings of the ICCSC´04. Moskva: IEEE, 2004.
  • Rok: 2004

Silicon-On-Insulator A Perspective on Low-Power, Low-Voltage Supervisory Circuits implemented with SOI Technology

  • Autoři: Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: Wireless Design and Development. 2004, 2004(5), 24-32. ISSN 1076-4240.
  • Rok: 2004
  • Pracoviště: Katedra teorie obvodů
  • Anotace:
    The magic term of SOI is attracting a lot of attention in the design of high-performance circuits. SOI offers speed, reliability and hardness beyond traditional technologies. SOI's performance parameters can be attributed largely to overall capacitance reduction as well as lower SOI device leakage. This creates the ideal opportunity for implementing SOI in sophisticated IC designs operating under LP-LV conditions. The focus of this article is to present an overview of SOI technology applied to design of a special class of ultra LP-LV devices - supervisory circuits. Such circuits are emerging as prime candidates for development using advanced SOI technology processes.

Switched-Capacitor and Switched-Current Circuits Suitable for Analogue Communication Front-Ends

  • Autoři: Maršík, J., Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Digital Technologies 2004. Žilina: Žilinská univerzita, 2004. pp. 18-21. ISBN 80-8070-334-5.
  • Rok: 2004

A Versatile Structure of S3I-GGA-casc Switched-Current Memory Cell with Complex Suppression of Memorizing Errors

High Performance Approach to Algorithmic A/D Converter Using New Types of Switched-Current Memory Cells

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Drechsler, P.
  • Publikace: Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003. p. 101-105. ISBN 0-08-044130-0.
  • Rok: 2003

High Precision S31-GGA-Case Memory Cell Structure Suitable for Versatile Use in Switched-Current Circuits

  • Autoři: Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: Digital Communications '03. Žilina: EDIS-vydavatelstvo ŽU, 2003. pp. 69-74. ISBN 80-8070-165-2.
  • Rok: 2003

A New Type of Universal Functional Block Suitable for Circuits Derived by Adjoint Transformation

  • Autoři: Martinek, P., Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: ICCSC'02 1st IEEE International Conference on Circuits and Systems for Communications - Proceedings. St. Petersburg: Saint-Petersburg State Technical University, 2002. pp. 74-77. ISBN 5-7422-0260-1.
  • Rok: 2002

Nový funkční blok pro obvody v proudovém módu

  • Autoři: Martinek, P., Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: Práce a štúdie Žilinskej univerzity. Žilina: Žilinská universita, Elektrotechnická fakulta, 2002. pp. 53-64. ISBN 80-7100-913-X.
  • Rok: 2002

Comparison of SI Memory Cells

  • Autoři: Martinek, P., Drechsler, P., Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: Conference Proceedings of the 11th International Czech-Slovak Scientific Conference. Brno: VUT v Brně, FEI, Ústav radioelektroniky, 2001. pp. 344-347. ISBN 80-214-1861-3.
  • Rok: 2001

High Precision Switched-Current Memory Cells and Their Implementation in a 8-bit Algorithmic A/D converter

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Drechsler, P.
  • Publikace: ECS'01 Conference Proceedings. Bratislava: STU v Bratislave, 2001. pp. 105-108.
  • Rok: 2001

GIC-Based Two-Amplifier Biquad Using Transimpedance Amplifiers

  • Autoři: Ing. Ondřej Šubrt, Ph.D., Martinek, P.
  • Publikace: Radioelektronika 2000 - Conference Proceedings. Bratislava: STU v Bratislave, FEI, 2000. pp. I-23-I-26. ISBN 80-227-1389-9.
  • Rok: 2000

Operační zesilovače s proudovou zpětnou vazbou

  • Autoři: Ing. Ondřej Šubrt, Ph.D.,
  • Publikace: Sdělovací technika. 2000, 2000(11(12)), 16(23)-19(25). ISSN 0036-9942.
  • Rok: 2000

Za stránku zodpovídá: Ing. Mgr. Radovan Suk