Ing. Petr Zakopal

Many electric drives, such as railway traction machines, are designed to be operated in an overmodulation region and in six-step mode, where the motor voltage waveform is distorted by low-order harmonics. The Selective Harmonic Elimination (SHE) method is an effective solution to reduce these unwanted harmonics. The SHE algorithm requires solving complex transcendental equations, traditionally tackled using algebraic or genetic algorithms. Historically, these equations were pre-solved, and the resulting switching angles were incorporated into microprocessors through Look-Up Tables (LUTs) and were selected based on the reference voltage. However, with the decreasing cost of electronic components, Field-Programmable Gate Arrays (FPGAs) have become a viable option for real-time computation of these equations. This paper validates the effectiveness of the SHE method in the common three-phase two-level Voltage Source Inverter (VSI) by implementing an off-line FPGA-in-the-Loop setup, integrated with MATLAB ® and Simulink ® environments, where the VSI and load are modeled. The Verilog FPGA computational modules designed in this paper were rigorously simulated and, upon achieving successful results in behavioral simulations, they were synthesized and deployed on a development board featuring a System on Chip (SoC) with an integrated FPGA.

The increasing popularity of electric drives employing an isolated dual-inverter (DI) topology is motivated by their superior DC-link voltage and power utilization, fault-tolerant operation, and potential for multilevel operation. These attributes are significant in battery-powered transportation, such as electric vehicles and aviation. Given the considerable freedom in modulation and control of the DI topology, this paper researches the impact of reference voltage vector distribution between the two individual inverters. The study also evaluates the influence of two well-established asynchronous modulation strategies—Space Vector PWM (SVPWM) and Depenbrock’s Discontinuous Modulation (DPWM1). Since simulation tools nowadays play a crucial role in power electronics design and concept verification, the results are based on extensive and detailed models in Matlab/Simulink. Employing the basic field-oriented control of a 12 kW induction motor with precisely parameterized SiC switching devices for accurate loss calculation, this research reveals the possibility of significant energy savings at multiple operating points. Notably, optimal efficiency is achieved when one inverter operates up to half of the nominal speed while the other solely establishes a neutral point for the winding. Moreover, the results highlight DPWM1 as a superior strategy for the DI topology, showcasing reduced converter losses. Overall, it is shown that the system’s losses can be significantly reduced just by the design of the voltage vector distribution in the drive’s operating range and the modulation strategy selection.

The dual-inverter topology is a key solution for high-performance motor drives, offering reliability and efficient DC-bus voltage utilization. This paper focuses on the isolated DC source configuration, known for its fault tolerance and suitability for applications like electric vehicles. Unlike common DC source setups, it eliminates the zero-sequence current path. This study explores the harmonic properties of popular carrier-based asynchronous modulation techniques (SVPWM, DPWM1, and DPWM2) in dual-inverter systems. While these techniques are well-studied in conventional inverters, their behavior in dual-inverter setups remains underexplored. The investigation includes different reference vector distributions and compares results with conventional inverters. The findings enhance our understanding of harmonic behavior in dual-inverter configurations, providing insights for optimizing motor drives and power electronics applications.

To address the gap in the tooling software for verifying Field Programmable Gate Array (FPGA) design, this paper introduces a Verilog implementation of a fully synthesizable unit for monitoring values of internal wires and registers. The unit samples an arbitrary number of internal signals and packages them into a Universal Asynchronous Receiver Transmitter (UART) message. Even when analysing multiple bit values only three FPGA board pins are required to transmit and receive messages using UART, in contrast to the conventional hardware logic analyzers where numerous pins are needed. The message is then sent from the FPGA to the Real-Time Monitor (RTM) application running on a host PC. Developed using the Rust programming language, the application ensures reliability, performance, memory safety, and efficiency. The resource utilization of the unit, deployed on the Gowin GW1NR-9 27 MHz chip, is presented. The unit, along with the RTM application, can be efficiently utilized for verifying arbitrary Verilog designs or employing them as an acquisition or monitoring hardware-software product.

The Dual-Inverter (DI) emerges as a viable solution to address the ever-growing demands of electric drives, encompassing fault tolerance capability, waveform quality, superior DC-bus voltage utilization, and multilevel operation. The DI with isolated DC sources eliminates the path for zero sequence current (ZSC), thereby enabling the implementation of various modulation strategies. This paper introduces two bus-clamping modulation strategies aimed at minimizing switching losses for DI with isolated DC sources. The effectiveness of these modulation strategies is validated using a DI model in the MATLAB/Simulink environment, incorporating SiC MOS-FETs transistors parameterized in accordance with the manufacturer’s datasheet. An induction machine with a rated power of 12 kW serves as the load for DI.

The Dual Inverter (DI) stands out as an optimal solution for electric drives and aviation, offering multilevel capabilities, high fault tolerance, waveform quality, and efficiency. Particularly, in configurations with isolated DC sources, a diverse array of modulation techniques can be effectively implemented. This paper compares the 60 ◦ Discontinuous Pulse-Width Modulation (DPWM)–well established technique for conventional two-level inverters, against the proposed Near State Pulse-Width Modulation (NSPWM) for DI, specifically examining their impact on switching losses. The assessment relies on a comprehensive MATLAB/Simulink model of the DI, incorporating SiC MOSFETs transistors parameterized in accordance with the manufacturer’s specifications. Additionally, a 12 kW squirrel cage induction motor is employed as the load for simulation purposes.