Ing. Dalibor Barri, Ph.D.

This paper presents an interesting phenomenon related to the effective threshold voltage changes (δVth,eff) in the diamond layout shape MOS transistors (DLS MOSFETs). Besides it, its analytical expression is presented here for the first time. The analytical approximative expression has been defined based on the results of the 3-D TCAD simulations for the different effective aspect ratio (W/L)eff and different angle α of DLS MOSFET. The effective aspect ratio has been set to 2.0, 1.5, 1.0, 0.5 with the angle α varied from 180° to 80° with the step 20°. Furthermore, for purpose to verify the 3-D TCAD simulation results and measurement results, 1 124 samples were fabricated, which were proportionally divided into rectangle layout shape (RLS) MOSFETs and DLS MOSFETs with the angles α equal to 120°, 100°, and 80°. All the samples have been fabricated in the 160 nm BCD technology process. The mentioned phenomenon described by the proposed expression fits the measured data with a very high level of accuracy equal to 99.995 %. Thus, the presented analytical expression proves its quality. Thanks to the high level of the expression quality, the given expression is recommended to use for the analog designs with high-level precision requests and DLS MOSFET components.

This paper introduces the latest modern automatized advanced measurement flow of the diamond layout shape MOS transistors (DLS MOSFETs) as well as the rectangular layout shape (RLS) MOSFETs directly on a wafer. There are presented photos of the DLS MOSFET, from the highest level of the wafer down to the lowest level of the wafer, where each photo is individually commented. The next part of this article presents each item of the proposed measurement flow, such as an air compressor, temperature forcing system, probe cards, and precision semiconductor parameter analyzer. Also, there is shown, a photo of the probe card used for the measurement, as well as planning of its needles. Besides others, there is describe four-points measurement strategy, and the last part of this paper recommends the minimum number of measurements in order to obtain relevant data. Finally, the measured data is compared with a theoretic analytical expression

This article introduces an innovative approach that describes the drain–source current improvements of MOS transistors. It is based on the geometrical modification of MOSFET’s channel from a rectangular layout shape (RLS) into a diamond layout shape (DLS). In this way, the drain–source current enhancement is increased up to 11% for the DLS MOS transistors with an effective aspect ratio (W/L)eff equal to 2.0 and an angle set to 80. Moreover, we present the comparison of 3-D TCAD simulations data, analytical model data based on Schwarz–Christoffel transformation (SCT), and measurement data given by the measurement of the MOS transistors fabricated in the Bipolar- CMOS-DMOS (BCD) 160-nm technology process. For this purpose, there have been fabricated 1124 samples, which were proportionally divided into RLS MOSFETs and DLS MOSFETs with the angles equal to 120, 100, and 80. For all studied aspect ratios, the presented model has an excellent analytic description in comparison with the 3-D TCAD simulation results with an error lower than 3%. So, it proves the quality of the analytical model based on the SCT approach and it is the recommended approach to use also for modeling other MOSFET gate layout shapes.

This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, until today no precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40% area reduction. The second MOSFET with the simpler orthogonal metal interconnections allows saving more than 20% area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.

With increasing demands on design and optimization of analog circuits in real applications, a limited number of algorithms for practical use have been presented. The drawbacks of already existing standard algorithms are in a possibility to stagnate in a not optimal solution and also big time consumption. These drawbacks have been overcome by our new proposed algorithm STOHE. The new algorithm is a combination of a STOchastic and HEuristic algorithms. As the stochastic respectively heuristic algorithm was chosen differential evolution algorithm respectively simplex algorithm. The algorithm has been verified by the design and optimization of an active OTA-C filter where the standard approach fails.

In the first part of this article, we have proposed an innovative approach to improve the drain current model of the MOSFETs implemented with the diamond layout style (DLS), regarding the longitudinal corner effect (LCE). The proposed model is more accurate than a previous model compared to 3-D TechnologyComputer-AidedDesign (3-D TCAD) simulation results. The new model has an innovative analytical description based on a conformal mapping theory. As a conformal mapping, there has been chosen a Schwarz–Christoffel transformation (SC). The maximal deviation values of the aspect ratio calculated by LCE are in the range from −27% to +38%. In counterpart with the new SC analytical description of DLS, the maximal deviation values are in the range from 0% to −5.5%. The second part of this article describes improvements in the electrical performance of the N-MOSFET components by using DLS counterpart to traditional rectangular layout style (RLS). Both layout style DLS, RLS, respectively, have the same process settings, as well as they are keeping the same gate area A, and an aspect ratio width to length W/L to preserve the same input conditions for their analysis. The maximal drain current increasing for the simulated DLS MOS transistor is over 20% for effective aspect ratio (W/L)eff equal to 2.0 and the angle is set to 60 grads. The presented model has a very good analytic description with the error level lower than 3%.

In this paper, we have analyzed the hump effect of polysilicon planar NMOS transistors. The hump effect caused by boron segregation makes a negative effect on transfer characteristic in the sub-threshold region of high voltage transistors. Therefore, we have analyzed the hump effect for several geometries, where various physical parameters have been lengths of MOS transistors, and gate thicknesses oxide of MOS transistors. Moreover, it has been studied for different simulation parameter. As the simulation parameters have been various gate-source voltages VGS, and bulk-source voltage VBS. In order to respect the hump effect in circuit level simulations, there has been verified a macromodel of the MOS transistor with the hump effect. All simulations have been run by the 3D TCAD Silvaco simulation tool.

With the increasing demands for design and optimization of analog integrated circuits (IC) in practical applications, a few of theoretical and practical algorithms for design and optimization of IC have been proposed. In this paper is presented a new DESA algorithm (Differential Evolution and Simplex Algorithm) that is based on the stochastic and heuristic algorithm. The combination of the two different algorithms bring a very powerful algorithm for design and optimization of any analog integrated circuits such is operation amplifier, current mirror or a complex structure as is OTA-C filter. As the reference an analog block was chosen as an active low-pass OTA-C filter.

A true random number generator (TRNG) with time multiplexed metastability-based sources of randomness, presented in this paper, is capable of generating random bit sequences formed from noise present in the electronic circuit. An incorporated time multiplexer interleaves digitized random signals coming from sources of randomness and increases output data rate. The proposed TRNGwas fabricated in a STMicroelectronics 130 nm bulk CMOS technology on an area of 0.029mm2. The quality of all random bit sequences has been verified by the FIPS and NIST statistical test suites. The fabricated TRNG generates random bit sequences up to the data rate of 20 Mb/s without any corrective mechanisms at power consumption of 72.48 uW. The changing environmental conditions do not influence the quality of random bit sequences.

In power MOSFETs devices can be recognized trends to replace planar gate by trench gate structures. The power devices with planar gates are simplier to fabricate and have higher maturity than non-planar power MOSFETs. In contrast Trench MOSFETs have a better performance but are more complex to fabricate and due to this have lower maturity. Proposed paper describe two new trench MOSFET structures with different gate patterns with optimized drain to source to On resistance. In general, for power MOSFET’s structures comparison the specific On resistance on area is used. This paper uses a normalized gate perimeter of element pattern, as an alternative figure of merit for a different trench MOSFET structure comparison because it is proportional to channel width and to drain to source resistance. Advantages and drawbacks of proposed new power MOSFETs structures are described.

This paper describes a new methodology how to evaluate systematic mismatch due to inhomogeneous parameter gradient in IC fabrication process for passive and active devices. The gradient sensitivity is discussed for both linear and nonlinear (nth-order) parameter gradients. Effect of the threshold gradients is simulated for the current mirror in simple layout pattern. Simulation results show a significant impact gradients angles through the active area for the layout pattern for the realization of the precise current mirror. The realized structure can be not only current mirror but also other sensitive blocks as a differential pair, resistor divider for voltage reference and many other analog circuit blocks. This paper also refers two mismatch definitions, systematic errors (gradient effects) and random errors.